Generally, the present disclosure pertains to power savings in electronic circuitry, for example, as practiced in clock management for a display subsystem as may be found in a personal computer (PC) or laptop PC.
FIG. 1 is a generalized block diagram of a computer system 100 in the prior art. In the computer system 100, central processing unit (CPU) 105 communicates via bus interface 110 to system memory 115. I/O interface 130 receives user input from one or more user input devices 135 (e.g., keyboard, mouse) and forwards the input to CPU 105. Visual output is provided on display device 145 (e.g., a CRT or LCD monitor) by way of graphics subsystem 140. System disk 120 (e.g., hard drive) is connected to I/O interface 130 or bus interface 110.
Clock generator 150 supplies clocks at a variety of frequencies to the various components of computer system 100. For example, clock generator 150 may provide a number of different clocks (e.g., at different frequencies) to drive the various hardware circuits within graphics subsystem 140. Clock generator 150 may supply a digital-to-analog converter (DAC, not shown) in graphics subsystem 140 with one or more clocks so that the DAC can generate an analog signal to display device 145, while clock generator 150 may also supply another circuit component such as I/O interface 130 with other clocks. The clocks are needed so that the various hardware circuitry in computer system 100 may perform their respective functions.
However, at any point in time, some portions of the circuitry in computer system 100 may be idle and not performing a needed function. While the circuitry is idle, computer system 100 may disable clocks to the idle circuitry in order to save power. For example, to extend battery life where computer system 100 is a laptop PC, a software component running on CPU 105 may command clock generator 150 to disable one or more of the clocks supplied to the idle circuitry.
However, providing a software component in computer system 100 to control enabling and disabling of clocks supplied by clock generator 150 has limitations. For example, providing a clock management function in a software component increases the overall complexity of the software running on CPU 105. Further, software intervention incurs delay, because it may take a relatively long time for the software to determine that a portion of the circuitry in computer system 100 is idle, determine whether clocks to the idle circuitry may be safely disabled, and then send commands or signals to clock generator 150 to disable the clocks.
Additionally, a software component running on CPU 105 may not always be “aware” of the exact state of the hardware in computer system 100. Therefore, there may be some inefficiency in deciding which clocks to disable or uncertainty as to when the clocks may be safely disabled. In an egregious case, software can “hang” or crash if one software component has disabled a portion of logic and another software component tries to write to the disabled logic. In some circumstances it may be possible for software to read the status of the hardware before writing to it, but providing such mechanisms increases the complexity of both the software and the hardware in computer system 100.